Hexagon architecture support by androm3da · Pull Request #107122 · zephyrproject-rtos/zephyr

androm3da · 2026-04-10T19:40:09Z

This patch series introduces architecture support for Qualcomm's Hexagon DSP processor to Zephyr.

The Hexagon architecture is a VLIW DSP architecture used in Qualcomm SoCs like SnapDragon and DragonWing. They're currently used for functions such as: Compute DSP / NPU, Audio DSP, Cellular modem, and more.

https://en.wikipedia.org/wiki/Qualcomm_Hexagon

For the sake of portability among DSP generations, we're creating a zephyr port that depends on the Hexagon Virtual Machine Specification. This is unfortunately unlike other architectures but perhaps strikes the best compromise for consistency's sake when new DSP generations make changes to the system architecture. This is the same approach we took for the linux kernel port to Hexagon.

The initial target is a QEMU-based virtual platform.

The Clang/LLVM and Rust/LLVM toolchains can target Hexagon. No modern gcc toolchain exists with support for Hexagon.

androm3da · 2026-04-10T19:40:36Z

Sorry -- I realize it might be a bit premature to lump this into a single PR. I'll break it down into PRs for some of these commits that should land independently. I'll cut the hexagon-specific bits down into whatever size is suitable/reasonable for the community to accept at-a-time.

cc @quic-mliebel @ChidvilasYQC

github-actions · 2026-04-10T19:41:49Z

The following west manifest projects have changed revision in this Pull Request:

Name	Old Revision	New Revision	Diff

✅ All manifest checks OK

Note: This message is automatically posted and updated by the Manifest GitHub Action.

henrikbrixandersen · 2026-04-11T22:13:21Z

Sorry -- I realize it might be a bit premature to lump this into a single PR. I'll break it down into PRs for some of these commits that should land independently. I'll cut the hexagon-specific bits down into whatever size is suitable/reasonable for the community to accept at-a-time.

Adding a description to the PR would be a good place to start.

androm3da · 2026-04-12T00:20:29Z

Sorry -- I realize it might be a bit premature to lump this into a single PR. I'll break it down into PRs for some of these commits that should land independently. I'll cut the hexagon-specific bits down into whatever size is suitable/reasonable for the community to accept at-a-time.

Adding a description to the PR would be a good place to start.

You're right -- thanks. Done.

nordicjm

an incredibly quick/brief check

nordicjm · 2026-04-13T08:13:32Z

+#include <zephyr/arch/hexagon/arch.h>
+
+/* Board-specific initialization */
+static int qemu_hexagon_init(void)


nordicjm · 2026-04-13T08:14:01Z

+set(QEMU_FLAGS_${ARCH}
+  -machine virt
+  -m 4G
+  )


misaliged bracket line 11, fix in whole PR

nordicjm · 2026-04-13T08:14:56Z

+CONFIG_LLVM_USE_ELD=y
+
+# System configuration
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000


line 23 -> set in soc Kconfig.defconfig file and get from dt using dts functions

nordicjm · 2026-04-13T08:15:14Z

+CONFIG_SRAM_BASE_ADDRESS=0xa0000000
+CONFIG_PICOLIBC=y


these seem superfluous/wrong place

nordicjm · 2026-04-13T08:15:19Z

+# Memory configuration
+CONFIG_MAIN_STACK_SIZE=2048
+CONFIG_IDLE_STACK_SIZE=2048
+CONFIG_ISR_STACK_SIZE=2048
+CONFIG_HEAP_MEM_POOL_SIZE=16384


nordicjm · 2026-04-13T08:15:47Z

+# SPDX-License-Identifier: Apache-2.0
+
+check_set_linker_property(TARGET linker PROPERTY base
+                          ${LINKERFLAGPREFIX},--gc-sections


misindentation, it is 2 spaces

nordicjm · 2026-04-13T08:16:36Z

+
+config SOC_SERIES
+	default "" if SOC_QEMU_HEXAGON_VIRT
+
+config SOC_FAMILY
+	default "" if SOC_QEMU_HEXAGON_VIRT


nordicjm · 2026-04-13T08:16:42Z

+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+
+config SOC_QEMU_HEXAGON_VIRT
+	bool "QEMU Hexagon Virtual Machine"


this is not valid for hwmv2

nordicjm · 2026-04-13T08:17:03Z

+void soc_early_init_hook(void)
+{
+	/* SoC-specific early initialization */
+}


nordicjm · 2026-04-13T08:17:43Z

+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+
+set(SUPPORTED_EMU_PLATFORMS qemu)
+


file to go unless line 4 is seen to be actually doing anything?

Add build system infrastructure for the Hexagon architecture port: - arch/Kconfig, archs.yml: register hexagon in the arch list - arch/hexagon/{CMakeLists.txt,Kconfig,defconfig}: top-level arch build - arch/hexagon/core/{CMakeLists.txt,Kconfig}: core build and config - arch/hexagon/core/offsets/offsets.c: kernel offset definitions - soc/qemu/hexagon/{CMakeLists.txt,linker.ld}: SoC build and linker script - include/zephyr/{linker,toolchain}: hexagon hooks for linker output format and toolchain macros Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

Add public and private header files for the Hexagon architecture: Public API: - arch.h: architecture interface (IRQ locking, syscall, nop, etc.) - arch_inlines.h, error.h, exception.h, thread.h Private headers: - hexagon_vm.h: Hexagon VM operations and trap interfaces - irq.h, irq_connect.h: interrupt management - kernel_arch_data.h, kernel_arch_func.h: kernel integration - offsets_short_arch.h, thread_stack.h: thread/stack layout Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

Add the core runtime implementation for the Hexagon architecture: - hvm_event_vectors.S: HVM guest event vector base (GEVB) with reset, exception, trap0, and interrupt entry points - event_handlers.S: EVENT_ENTRY/EXIT macros for saving and restoring context on interrupt and exception entry - switch.S: arch_switch() context switch and thread start trampoline - irq_manage.c: interrupt dispatcher - intc.c: VM-based interrupt controller - cpu_idle.c: idle implementation using vmsetie with self-posted timer - vmsetie_cached.c: cached IE state tracking for nested irq_lock/unlock - thread.c: thread initialization with fake switch frames - tls.c: thread-local storage using UGP register - fatal.c: fatal error handling and exception dump - prep_c.c: early C entry point Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

Pass --no-default-config to both compile and link phases. The Hexagon cross-toolchain ships a hexagon-unknown-none-elf.cfg that clang auto-discovers. It injects -nostdlibinc and -isystem <picolibc> before command-line flags, causing picolibc headers to shadow Zephyr's minimal libc headers and breaking all CONFIG_MINIMAL_LIBC builds (ZRESTRICT undefined, conflicting types). With the default config suppressed, supply -nostdlibinc and the picolibc include path explicitly so include search order is correct regardless of libc selection. Note: clang >= 23 no longer leaks host /usr/include into the Hexagon target search path (see llvm/llvm-project#188824). Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

sonarqubecloud · 2026-04-15T06:06:09Z

Quality Gate passed

Issues
7 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

github-actions bot added manifest manifest-picolibc DNM (manifest) This PR should not be merged (controlled by action-manifest) labels Apr 10, 2026

nordicjm requested changes Apr 13, 2026

View reviewed changes

androm3da added 9 commits April 14, 2026 21:59

soc: add support for QEMU hexagon virt machine

d0d7e02

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

boards: add QEMU hexagon board

470a262

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

cmake: add support for hexagon to LLVM

6d66166

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

hexagon: memory management

e75564c

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

hexagon: add timer functionality

1163069

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

androm3da force-pushed the bcain/hexagon_support branch from a819989 to 681e9f6 Compare April 15, 2026 05:34

github-actions bot removed manifest manifest-picolibc DNM (manifest) This PR should not be merged (controlled by action-manifest) labels Apr 15, 2026

		# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.

		set(SUPPORTED_EMU_PLATFORMS qemu)

		CONFIG_SRAM_BASE_ADDRESS=0xa0000000
		CONFIG_PICOLIBC=y

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