Projects implemented in Spartan3 and Spartan3e for the Digital Systems class
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Oct 14, 2020 - Verilog
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fpga-verilog
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This repository contains Verilog HDL implementations of Half Adders, Full Adders, and 4-bit Adders, designed at three different abstraction levels: Gate Level, Dataflow Level, and Behavioral Level. These designs are fundamental to digital electronics, and this project showcases the versatility of Verilog in modeling and simulating digital circuits.
circuit-simulation verilog-hdl test-bench half-adder hardware-description-language digital-electronics full-adder verilog-project vlsi-design rtl-design arithmetic-operations fpga-verilog logic-circuit-design behavioral-modeling 4-bit-adder verilog-adders gate-level-design dataflow-design digital-circuit-simulation hdl-coding
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Aug 24, 2024 - Verilog
SHA1 Hardware Accelerator on Intel MAX 10 DECA using Nios II + SystemVerilog
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Mar 8, 2026 - C
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