de10-lite

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Here are 39 public repositories matching this topic...

jeferal / Pong-FPGA

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Pong game on FPGA Max 10 DE10-Lite, written in VHDL.

fpga pong vhdl vga vga-driver digital-electronics de10-lite max10

Updated Oct 14, 2021
VHDL

JosiahMendes / Autonomous-Rover

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The Design and Implementation of an Autonomous Mars Rover that has full mapping, remote control and power management capabilities.

nodejs arduino reactjs rover mars optical-flow autonomous-driving smps de10-lite esp32-arduino

Updated Jun 17, 2021
C

timot3 / ECE385-Ethernet

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ECE 385 Final Project -- Ethernet on MAX10 DE10-Lite FPGA and Nios II soft processor

fpga ethernet ethernet-shield nios2 de10-lite nios-ii

Updated Dec 13, 2021
Verilog

RomeoMe5 / De10-Lite_HDL_GPS

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Simple verilog project with ability to connect to GPS module using UART and parse NMEA coordinates using finite state machine

gps ubx uart hse nmea quartus miem de10-lite terasic-de10-lite nmea-0183 rtcm terasic neo-6

Updated Mar 21, 2019
Verilog

WassimHedfi / FPGA-Projects

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This repository showcases the projects I developed for the DE10-Lite board as part of the "FPGA Capstone: Building FPGA Projects" course on Coursera.

c fpga vhdl verilog modelsim quartus-prime de10-lite fpga-design programmable-logic-design softcore-processor-design

Updated Sep 26, 2024
Verilog

FedorChervyakov / de10lite-hello-vga

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VGA demo on the Terasic DE10-Lite FPGA board

fpga makefile vga quartus de10-lite

Updated Jun 6, 2021
VHDL

pa-tiq / vending_machine

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fpga verilog quartus-prime quartus de10nano de10-lite de10-nano verilog-project quartus-18-1

Updated Jul 14, 2019
Verilog

protocol66 / FPGADefender

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VHDL implementation of the Defender arcade game for DE-10 Lite FPGA. For ECE 4110 project.

fpga-game de10-lite

Updated Dec 2, 2021
VHDL

LockBall / floatfixlib_VHDL1993

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ieee_proposed with names changed to floatfixlib to be compatible with Quartus Prime Lite and support fixed, float, etc.

vhdl modelsim float fixed quartus de10-lite questa floatfixlib ieee-proposed

Updated Oct 25, 2023
VHDL

Simulation platform that enables VHDL-style C++ coding. VCD generation for easy debug. VHDL code generation using C preprocessor. Simple risc-V rv32i SoC example, + Risc-V test suite and gcc bare-metal example. Linux (or WSL) / clang or gcc / risc-v toolchain / quartus required

c-plus-plus arduino simulator fpga vhdl rtl gtkwave risc-v vcd de10-lite vidor rtl-files rtl-generation

Updated May 29, 2021
C

Jjateen / Snake-Game-Verilog

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This repository showcases a Verilog-based Snake and Apple Game, developed for the ECL 106: Digital System Design with HDL course. Running on an Altera DE10-Lite FPGA board and displayed on a VGA monitor, players control a snake to collect apples while avoiding obstacles. The snake grows longer with each apple, making the game progressively harder.

fpga verilog quartus-prime de10-lite altera-fpga verilog-project

Updated Feb 5, 2025
Verilog

FedorChervyakov / de10lite-hello-adc

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ADC demo on the Terasic DE10-Lite board with MAX10 FPGA

fpga adc quartus de10-lite max10 quartus-linux

Updated Feb 7, 2021

jakujobi / BitBlaster_10bit_Processor

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Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.

fpga processor systemverilog processors digital-design quartus-prime quartus de10-lite processor-design jakujobi

Updated Dec 8, 2023
SystemVerilog

realchonk / quartus-make

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This is a template for projects using the Quartus Prime suite with the DE10-Lite FPGA board.

template makefile makefile-template template-project quartus-prime quartus de10-lite

Updated May 28, 2022
Verilog

franciscoengenheiro / ticket-machine-fpga

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Train ticket vending machine application designed for execution on an FPGA system. The application allows users to purchase tickets for various destinations and includes maintenance functionalities.

fpga circuits embedded-systems hardware-designs college-project ticket-vending-machine de10-lite signals-and-systems logical-circuits