ALTERA 10M08SAM153

VCC, GND, TXD and RXD

USB-TTL CP2102

STEPFPGA MAX10

https://github.com/Edragon/fpga_max10

https://github.com/Edragon/FPGA_MAX10-1

https://github.com/stepfpga/STEP-MAX10

chip Versions
10M08SCM - MAX10 M08 SCM
10M02SCM

10M08SAM - MAX10 M08 SAM 153

chip models note

08SCM - 8K logic elements

SC : Single supply - compact features
M : Micro FineLine BGA (MBGA)
153: MBGA Package Type 153 : 153 pins, 8 mm x 8 mm
C : Commercial (T = 0° C to 85° C)
8: FPGA Fabric Speed Grade
G : RoHS6

ALTERA10MO2SCM153

Core device: ALTERA10MO2SCM153
153-pin BGA package, pin pitch 0.5MM, chip size 8MM*8MM
2000 LE resources, 12KB user flash memory, 108KBIT RAM
Supports DDR2/DDR3L/DDR3/LPDDR2 memory
16 hardware multipliers
112 user GPIOs
3.3V power supply
Instant-on at power-up

On-board resources:

Two RGB tri-color LEDs
2 user LEDs
4-channel DIP switch
2 push buttons
36 user-expandable I/O
Supported development tool: ALTERA QUARTUS II
One Type-C interface One 10-PIN JTAG programming interface: Board size 52MM×18MM

ALTERA10M08SAM153

Core device: ALTERA10M08SAM153 153-pin BGA package, pin pitch 0.5MM, chip size 8MMX8MM
8000 LE resources, up to 172KB user flash memory, 378KBIT RAM
Supports DDR2/DDR3L/DDR3/LPDDR2 memory
24 hardware multipliers
112 user GPIOs
Instant-on at power-up
3.3V power supply
2 PLLs

Pin definition

ASEM-51 V1.2

https://plit.de/asem-51/

https://plit.de/asem-51/download.htm

ASEM-51 V1.2 Copyright (c) 1996 by W.W. Heinz

   MCS-51 Family Cross Assembler   A S E M - 5 1   V 1.2  

Z80 CPU with 8kB ROM and 8kB RAM

T80 CORE

https://opencores.org/projects/t80

https://github.com/freecores/t80

Wallner, Daniel
MikeJ

TV80 CORE

https://opencores.org/projects/tv80

Hutchison, Guy
M. Harte, Howard

https://github.com/hutch31/tv80/tree/master
https://github.com/freecores/tv80

T51 mcu

https://opencores.org/projects/t51/

2001-2002 Daniel Wallner
2004-2005 Andreas Voggeneder

https://github.com/freecores/t51

C51ASM from ATMEL

https://www.microchip.com/en-us/development-tool/C51ASM

Oregano Systems 8051 IP core

https://www.oreganosystems.at/products/ip-cores/8051-ip-core

The 8051 IP Core had been developed in cooperation with the Vienna University of Technology. This IP core is binary compatible to the well known 8051 processor from Intel. The Oregano Systems 8051 IP core is available as a parameterizable, synthesizable circuit description (VHDL).

The Oregano Systems 8051 IP core offers faster program execution compared to the original 8051 devices due to an optimized processor’s architecture. Additionally, the Oregano Systems 8051 IP core can be parametrized. The Oregano Systems 8051 IP Core is available free of charge even for industrial applications under the LGPL (Lesser General Public License).

https://www.oreganosystems.at/application/files/9215/3313/6321/mc8051_design_v1.6.zip