About Me:
- 🔭 I'm currently studying EE (Electronic Engineering) at UCAS
- 📫 How to reach me: dingyi233@mails.ucas.ac.cn
- ⚡ Fun fact: I used to be a semi-professional soccer player as a national level two athlete.
- 🌱 I am currently learning about tranceivers, with a particular focus on key components such as VCO, PLL, and CDR.
My Technology Stack:
- LaTex
- MATLAB
- C Programming
- MCU (Micro-Controller Unit)
- PCB Layout
- Analog Circuit Design
- LTspice (ANALOG DEVICES)
- Cadence Virtuoso
- Analog IC Design (OPA, OTA, BGR, LDO, etc.)
- Mixed-Signal IC Design (DAC, VCO, PLL, etc.)
- Verilog, Verilog-A/AMS
I'm a Night 🦉
🌞 Morning 86 commits ██░░░░░░░░░░░░░░░░░░░░░░░ 06.28 %
🌆 Daytime 450 commits ████████░░░░░░░░░░░░░░░░░ 32.87 %
🌃 Evening 439 commits ████████░░░░░░░░░░░░░░░░░ 32.07 %
🌙 Night 394 commits ███████░░░░░░░░░░░░░░░░░░ 28.78 %
📅 I'm Most Productive on Friday
Monday 206 commits ████░░░░░░░░░░░░░░░░░░░░░ 15.05 %
Tuesday 170 commits ███░░░░░░░░░░░░░░░░░░░░░░ 12.42 %
Wednesday 166 commits ███░░░░░░░░░░░░░░░░░░░░░░ 12.13 %
Thursday 215 commits ████░░░░░░░░░░░░░░░░░░░░░ 15.70 %
Friday 229 commits ████░░░░░░░░░░░░░░░░░░░░░ 16.73 %
Saturday 168 commits ███░░░░░░░░░░░░░░░░░░░░░░ 12.27 %
Sunday 215 commits ████░░░░░░░░░░░░░░░░░░░░░ 15.70 %
📊 This Week I Spent My Time On
💬 Programming Languages:
Markdown 23 hrs 43 mins █████████████████████████ 100.00 %
🐱💻 Projects:
GH.YiDingg 23 hrs 43 mins █████████████████████████ 100.00 %
I Mostly Code in TeX
TeX 4 repos ███████░░░░░░░░░░░░░░░░░░ 28.57 %
C 4 repos ███████░░░░░░░░░░░░░░░░░░ 28.57 %
MATLAB 3 repos █████░░░░░░░░░░░░░░░░░░░░ 21.43 %
JavaScript 2 repos ████░░░░░░░░░░░░░░░░░░░░░ 14.29 %
Verilog 1 repo ██░░░░░░░░░░░░░░░░░░░░░░░ 07.14 %
Last Updated on 2026.04.20 19:38 UTC
